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Table 1. Signal List by Ball Number (continued)
Power-
I/O Multiplexing Mode 2
Ball
Number
Signal Name
On
Reset
Value
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Ref.
Supply
C21
V DDSXP
V DDSXP
C22
SRIO_TXD3/GE2_SGMII_T
SGMII support on SERDES is enabled by Reset Configuration Word
V DDSXP
X
C23
C24
C25
C26
C27
C28
D1
V DDSXP
MDQ26
MDQ25
MDM3
GND
MDQ24
Reserved 1
V DDSXP
V DDDDR
V DDDDR
V DDDDR
GND
V DDDDR
—
D2
GE2_RD1/PCI_AD28
Ethernet 2
PCI
Ethernet 2
V DDGE2
D3
GND
GND
D4
TDM7TDAT/GE2_TD3/
TDM
PCI
Ethernet 2
UTOPIA
V DDGE2
PCI_AD3/UTP_TMD
D5
TDM7RDAT/GE2_RD3/
TDM
PCI
Ethernet 2
UTOPIA
V DDGE2
PCI_AD1/UTP_STA
D6
GE1_RD0/UTP_RD2/
UTOPIA
Ethernet 1
PCI
UTOPIA
Ethernet 1 UTOPIA
V DDGE1
PCI_CBE2
D7
TDM7TCLK/GE2_TCK/
TDM
PCI
Ethernet 2
UTOPIA
V DDGE2
PCI_IDS/UTP_RER
D8
Reserved 1
—
D9
Reserved
1
—
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
Reserved 1
Reserved 1
GND SXP
SRIO_TXD0
GND SXP
SRIO_TXD1
V DDSXC
Reserved 1
Reserved 1
GND SXP
—
—
GND SXP
V DDSXP
GND SXP
V DDSXP
V DDSXC
—
—
GND SXP
D20
SRIO_TXD2/GE1_SGMII_T
SGMII support on SERDES is enabled by Reset Configuration Word
V DDSXP
X
D21
GND SXP
GND SXP
D22
SRIO_TXD3/GE2_SGMII_T
SGMII support on SERDES is enabled by Reset Configuration Word
V DDSXP
X
8
D23
D24
D25
D26
D27
D28
E1
GND SXP
MDQ23
V DDDDR
MDQ22
MDQ21
MDQS2
Reserved 1
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
GND SXP
V DDDDR
V DDDDR
V DDDDR
V DDDDR
V DDDDR
—
Freescale Semiconductor
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